Surprised nobody has mentioned the Pico2 boards (based on RP2350A or
RP2350B chips, instead of RP2040).
2x ARM cores plus 2x RISC-V cores (perm any 2 from 4)
150 MHz with FPU instead of 133MHz without
lower power consumption
more I/O pins (B model only?)
I really ought to buy a couple for tinkering ...
official boards not available yet, but 3rd party boards are, e.g.
<https://shop.pimoroni.com/products/tiny-2350?variant=42092638699603> ><https://shop.pimoroni.com/products/pga2350?variant=42092629229651>
On Sun, 11 Aug 2024 21:45:42 +0100, Andy Burns <usenet@andyburns.uk>
wrote:
Surprised nobody has mentioned the Pico2 boards (based on RP2350A or >>RP2350B chips, instead of RP2040).
2x ARM cores plus 2x RISC-V cores (perm any 2 from 4)
150 MHz with FPU instead of 133MHz without
lower power consumption
more I/O pins (B model only?)
I really ought to buy a couple for tinkering ...
official boards not available yet, but 3rd party boards are, e.g.
<https://shop.pimoroni.com/products/tiny-2350?variant=42092638699603> >><https://shop.pimoroni.com/products/pga2350?variant=42092629229651>
As of now, Digikey shows no stock on the Pico2 and doesn't recognize
the RP2350 chip as a product. Ditto Mouser.
The fast floats look great. I wonder how fast they are.
As of now, Digikey shows no stock on the Pico2
and doesn't recognize
the RP2350 chip as a product. Ditto Mouser.
The fast floats look great. I wonder how fast they are.
The RP2350 data sheet is 1347 pages!
Surprised nobody has mentioned the Pico2 boards (based on RP2350A orPimoroni Pico plus 2 is sitting on my desktop ready for me to play with
RP2350B chips, instead of RP2040).
2x ARM cores plus 2x RISC-V cores (perm any 2 from 4)
150 MHz with FPU instead of 133MHz without
lower power consumption
more I/O pins (B model only?)
I really ought to buy a couple for tinkering ...
official boards not available yet, but 3rd party boards are, e.g.
<https://shop.pimoroni.com/products/tiny-2350?variant=42092638699603> <https://shop.pimoroni.com/products/pga2350?variant=42092629229651>
Most interestingly enough, you can actually boot up with one RISCV core
and one ARM core, two RISCV cores or both ARM cores. Mixed processor
cores that'll be fun to see what we can do with that.
Single Stage to Orbit wrote:Perhaps someone really, really smart might figure out how to get all
Most interestingly enough, you can actually boot up with one RISCV
core and one ARM core, two RISCV cores or both ARM cores. Mixed
processor cores that'll be fun to see what we can do with that.
That's what I meant by "perm any 2 from 4", fun with the inter-CPU
doorbells ...
The RP2350 data sheet is 1347 pages!
On Sun, 11 Aug 2024 14:07:59 -0700
John Larkin <jjlarkin@highlandtechnology.com> wrote:
The RP2350 data sheet is 1347 pages!
The days of fitting an instruction set on a page or two are long
gone.
On Sun, 11 Aug 2024 14:07:59 -0700
John Larkin <jjlarkin@highlandtechnology.com> wrote:
The RP2350 data sheet is 1347 pages!
The days of fitting an instruction set on a page or two are long gone.
On Sun, 11 Aug 2024 14:04:36 -0700, John Larkin <jjlarkin@highlandtechnology.com> wrote:
On Sun, 11 Aug 2024 21:45:42 +0100, Andy Burns <usenet@andyburns.uk>
wrote:
Surprised nobody has mentioned the Pico2 boards (based on RP2350A or
RP2350B chips, instead of RP2040).
2x ARM cores plus 2x RISC-V cores (perm any 2 from 4)
150 MHz with FPU instead of 133MHz without
lower power consumption
more I/O pins (B model only?)
I really ought to buy a couple for tinkering ...
official boards not available yet, but 3rd party boards are, e.g.
<https://shop.pimoroni.com/products/tiny-2350?variant=42092638699603>
<https://shop.pimoroni.com/products/pga2350?variant=42092629229651>
As of now, Digikey shows no stock on the Pico2 and doesn't recognize
the RP2350 chip as a product. Ditto Mouser.
The fast floats look great. I wonder how fast they are.
The RP2350 data sheet is 1347 pages!
In comp.sys.raspberry-pi Ahem A Rivet's Shot <steveo@eircom.net> wrote:
On Sun, 11 Aug 2024 14:07:59 -0700
John Larkin <jjlarkin@highlandtechnology.com> wrote:
The RP2350 data sheet is 1347 pages!
The days of fitting an instruction set on a page or two are long
gone.
These days, when you've got a 1K+ page manual you know it's the actual manual. If it's 10 pages it's just a 'product brief' that shows some basic information about the chip but not nearly enough to program it (contact the OEM and they'll make you sign an NDA for the actual details, and maybe only if you're going to buy a million units).
Most of the time you can ignore huge chunks of the manual - if you never use the CAN bus transceiver, skip that section. But better to have the information there if you need it.
Theo
These days, when you've got a 1K+ page manual you know it's the actual manual. If it's 10 pages it's just a 'product brief' that shows some basic information about the chip but not nearly enough to program it
Andy Burns wrote:
2x ARM cores plus 2x RISC-V cores (perm any 2 from 4)
No according to what I have read. RISC or ARM. Not one of each,
As long as the silicon errata sheet isn’t 1000 pages!
TNP wrote [direct via email, not the group]It also says you can have mixed cores too, one of each. That looks like
Andy Burns wrote:
2x ARM cores plus 2x RISC-V cores (perm any 2 from 4)
No according to what I have read. RISC or ARM. Not one of each,
Section 3.9 of the datasheet says ...
"There are two processor sockets on RP2350, referred to as core 0 and
core 1 throughout this document. Each socket can be occupied either
by a Cortex-M33 processor (implementing the Armv8-M Main
architecture, plus extensions) or by a Hazard3 processor
(implementing the RV32IMAC architecture, plus extensions)."
On 12/08/2024 17:42, Phil Hobbs wrote:
As long as the silicon errata sheet isn’t 1000 pages!
That reminds me of only Intel's attempt at an ARM design; they were
tasked with updating the Strong ARM, instead they made the XScale which
was a complete dog of a core, and the errata alone was almost the size
ofthe complete SA110 manual.
Yes, they keep frying 13th gen and 14th gen with spurious voltageThat reminds me of only Intel's attempt at an ARM design; they were
tasked with updating the Strong ARM, instead they made the XScale
which was a complete dog of a core, and the errata alone was almost
the size ofthe complete SA110 manual.
When it comes to bugs in chips, Intel certainly have form.
On Mon, 2024-08-12 at 22:18 +0100, David Higton wrote:
That reminds me of only Intel's attempt at an ARM design; they were
tasked with updating the Strong ARM, instead they made the XScale
which was a complete dog of a core, and the errata alone was almost
the size ofthe complete SA110 manual.
When it comes to bugs in chips, Intel certainly have form.
Yes, they keep frying 13th gen and 14th gen with spurious voltage
spikes!
I've got a RISCV baremetal operating system I might bring up on this
device but looking at the datasheet for the RISCV processor used, it's
only got machine mode and user mode, no supervisor mode and no paging.
It does not even support any of the Sv pagetables so that's a
challenge.
Most interestingly enough, you can actually boot up with one RISCV core
and one ARM core, two RISCV cores or both ARM cores. Mixed processor
cores that'll be fun to see what we can do with that.
In message <v9dq6u$3epka$1@dont-email.me>
druck <news@druck.org.uk> wrote:
On 12/08/2024 17:42, Phil Hobbs wrote:
As long as the silicon errata sheet isn’t 1000 pages!
That reminds me of only Intel's attempt at an ARM design; they were
tasked with updating the Strong ARM, instead they made the XScale which
was a complete dog of a core, and the errata alone was almost the size
ofthe complete SA110 manual.
When it comes to bugs in chips, Intel certainly have form.
On 8/11/24 23:07, John Larkin wrote:
On Sun, 11 Aug 2024 14:04:36 -0700, John Larkin
<jjlarkin@highlandtechnology.com> wrote:
On Sun, 11 Aug 2024 21:45:42 +0100, Andy Burns <usenet@andyburns.uk>
wrote:
Surprised nobody has mentioned the Pico2 boards (based on RP2350A or
RP2350B chips, instead of RP2040).
2x ARM cores plus 2x RISC-V cores (perm any 2 from 4)
150 MHz with FPU instead of 133MHz without
lower power consumption
more I/O pins (B model only?)
I really ought to buy a couple for tinkering ...
official boards not available yet, but 3rd party boards are, e.g.
<https://shop.pimoroni.com/products/tiny-2350?variant=42092638699603>
<https://shop.pimoroni.com/products/pga2350?variant=42092629229651>
As of now, Digikey shows no stock on the Pico2 and doesn't recognize
the RP2350 chip as a product. Ditto Mouser.
The fast floats look great. I wonder how fast they are.
The RP2350 data sheet is 1347 pages!
read the part on how the build in buck converter needs a custom inductor >with polarity marking to work, and tell there is something seriously
wrong with it
On Mon, 12 Aug 2024 18:41:59 +0200, Lasse Langwadt <llc@fonz.dk>
wrote:
On 8/11/24 23:07, John Larkin wrote:
On Sun, 11 Aug 2024 14:04:36 -0700, John Larkin
<jjlarkin@highlandtechnology.com> wrote:
On Sun, 11 Aug 2024 21:45:42 +0100, Andy Burns <usenet@andyburns.uk>
wrote:
Surprised nobody has mentioned the Pico2 boards (based on RP2350A or >>>>> RP2350B chips, instead of RP2040).
2x ARM cores plus 2x RISC-V cores (perm any 2 from 4)
150 MHz with FPU instead of 133MHz without
lower power consumption
more I/O pins (B model only?)
I really ought to buy a couple for tinkering ...
official boards not available yet, but 3rd party boards are, e.g.
<https://shop.pimoroni.com/products/tiny-2350?variant=42092638699603> >>>>> <https://shop.pimoroni.com/products/pga2350?variant=42092629229651>
As of now, Digikey shows no stock on the Pico2 and doesn't recognize
the RP2350 chip as a product. Ditto Mouser.
The fast floats look great. I wonder how fast they are.
The RP2350 data sheet is 1347 pages!
read the part on how the build in buck converter needs a custom inductor >>with polarity marking to work, and tell there is something seriously
wrong with it
The polarized inducor is strange.
I'd expect that a small shielded
inductor would work fine. It is interesting to have a switching
regulator on a CPU chip... near a 12-bit ADC!
The Pi designs struggle to save pennies and microwatts, which not all
of us care about.
The Pi designs struggle to save pennies and microwatts, which not all of
us care about.
On 11/08/2024 22:32, Single Stage to Orbit wrote:
I've got a RISCV baremetal operating system I might bring up on this
device but looking at the datasheet for the RISCV processor used, it's
only got machine mode and user mode, no supervisor mode and no paging.
It does not even support any of the Sv pagetables so that's a
challenge.
The joys open "open source" CPUs with no standardised feature sets.
Most interestingly enough, you can actually boot up with one RISCV core
and one ARM core, two RISCV cores or both ARM cores. Mixed processor
cores that'll be fun to see what we can do with that.
I think they did that for all the people who keep insisting they
should move to the "new future" of RISC V. Now they can find out how
badly it compares to a contemporary ARM core.
druck <news@druck.org.uk> writes:
On 11/08/2024 22:32, Single Stage to Orbit wrote:
I've got a RISCV baremetal operating system I might bring up on
this device but looking at the datasheet for the RISCV processor
used, it's only got machine mode and user mode, no supervisor
mode and no paging. It does not even support any of the Sv
pagetables so that's a challenge.
Also no floating point, if I’ve understood correctly?
Yes the datasheet says the unused cores are gated off.The joys open "open source" CPUs with no standardised feature sets.
Most interestingly enough, you can actually boot up with one
RISCV core and one ARM core, two RISCV cores or both ARM cores.
Mixed processor cores that'll be fun to see what we can do with
that.
I think they did that for all the people who keep insisting they
should move to the "new future" of RISC V. Now they can find out
how badly it compares to a contemporary ARM core.
It’s a slightly odd device, isn’t it?
If you wanted to explore RISC-V then there’s more flexible options.
If you just wanted a microcontroller for something and didn’t care
too much about CPU architecture then the dual-architecture thing is
wasted. Two entire CPU cores that you don’t get to use.
On 11/08/2024 22:32, Single Stage to Orbit wrote:
I've got a RISCV baremetal operating system I might bring up on this
device but looking at the datasheet for the RISCV processor used, it's
only got machine mode and user mode, no supervisor mode and no paging.
It does not even support any of the Sv pagetables so that's a
challenge.
The joys open "open source" CPUs with no standardised feature sets.
Most interestingly enough, you can actually boot up with one RISCV core
and one ARM core, two RISCV cores or both ARM cores. Mixed processor
cores that'll be fun to see what we can do with that.
I think they did that for all the people who keep insisting they should
move to the "new future" of RISC V. Now they can find out how badly it compares to a contemporary ARM core.
---druck--
On Mon, 12 Aug 2024 19:43:38 -0700, John Larkin wrote:
The Pi designs struggle to save pennies and microwatts, which not all of
us care about.
There are products other than the Raspberry Pi available for those with
more money to thr^H^H^Hspend.
It’s a slightly odd device, isn’t it?
If you wanted to explore RISC-V then there’s more flexible options. If
you just wanted a microcontroller for something and didn’t care too much about CPU architecture then the dual-architecture thing is wasted. Two
entire CPU cores that you don’t get to use.
It's easy to write a core
On 13 Aug 2024 14:01:07 +0100 (BST)
Theo <theom+news@chiark.greenend.org.uk> wrote:
It's easy to write a core
I wish I could take that statement back to say 1975.
On Mon, 12 Aug 2024 19:43:38 -0700, John Larkin wrote:
The Pi designs struggle to save pennies and microwatts, which not all of
us care about.
There are products other than the Raspberry Pi available for those with
more money to thr^H^H^Hspend.
On Sun, 2024-08-11 at 21:45 +0100, Andy Burns wrote:
Surprised nobody has mentioned the Pico2 boards (based on RP2350A or
RP2350B chips, instead of RP2040).
2x ARM cores plus 2x RISC-V cores (perm any 2 from 4)
150 MHz with FPU instead of 133MHz without
lower power consumption
more I/O pins (B model only?)
I really ought to buy a couple for tinkering ...
official boards not available yet, but 3rd party boards are, e.g.
<https://shop.pimoroni.com/products/tiny-2350?variant=42092638699603>
<https://shop.pimoroni.com/products/pga2350?variant=42092629229651>
Pimoroni Pico plus 2 is sitting on my desktop ready for me to play with
it.
This beast also has 16MB of flashram and 8MB of PSRAM. I've also got a
SD card board and some headers I need to solder on to use with it.
I've got a RISCV baremetal operating system I might bring up on this
device but looking at the datasheet for the RISCV processor used, it's
only got machine mode and user mode, no supervisor mode and no paging.
It does not even support any of the Sv pagetables so that's a
challenge.
Most interestingly enough, you can actually boot up with one RISCV core
and one ARM core, two RISCV cores or both ARM cores. Mixed processor
cores that'll be fun to see what we can do with that.
Richard Kettlewell <invalid@invalid.invalid> wrote:
ItÆs a slightly odd device, isnÆt it?
If you wanted to explore RISC-V then thereÆs more flexible options. If
you just wanted a microcontroller for something and didnÆt care too much
about CPU architecture then the dual-architecture thing is wasted. Two
entire CPU cores that you donÆt get to use.
Microcontroller RISC-V cores are so small that I presume it's just thrown on >there as a test to see how things pan out. You can do a basic RV32 in a few >hundred lines of SystemVerilog and, if it doesn't have its own on-chip >memory, it takes pretty minimal area. It's the area for on-chip RAM, on-chip >flash, registers, caches and TLBs that costs.
It sounds like one of their devs had a hobby core on his github and they put >it on the chip just because they could. What I'm more interested in is what >QA they did on it and what tools they used. It's easy to write a core but >embarassing if it doesn't do what you think it does[1]. Perhaps the >'enabling/disabling' mechanism is a chicken bit to wall it off in case >something bad is discovered in it.
Theo
[1] https://ghostwriteattack.com/
On 13 Aug 2024 14:01:07 +0100 (BST), Theo
<theom+news@chiark.greenend.org.uk> wrote:
Microcontroller RISC-V cores are so small that I presume it's just thrown on >there as a test to see how things pan out. You can do a basic RV32 in a few >hundred lines of SystemVerilog and, if it doesn't have its own on-chip >memory, it takes pretty minimal area. It's the area for on-chip RAM, on-chip >flash, registers, caches and TLBs that costs.
It sounds like one of their devs had a hobby core on his github and they put >it on the chip just because they could. What I'm more interested in is what >QA they did on it and what tools they used. It's easy to write a core but >embarassing if it doesn't do what you think it does[1]. Perhaps the >'enabling/disabling' mechanism is a chicken bit to wall it off in case >something bad is discovered in it.
Theo
[1] https://ghostwriteattack.com/
Long term, the ARM license may be a liability.
On Tue, 13 Aug 2024 04:05:24 -0000 (UTC), Lawrence D'Oliveiro <ldo@nz.invalid> wrote:
On Mon, 12 Aug 2024 19:43:38 -0700, John Larkin wrote:
The Pi designs struggle to save pennies and microwatts, which not all of >>> us care about.
There are products other than the Raspberry Pi available for those with
more money to thr^H^H^Hspend.
I like the Pi for more reasons than the cost. The chips have long-term availability guarentees, the documentation is excellent, and there are zillions of kids out there who are familiar with the Pi culture.
Even ignoring the 70 cent price, the RP2040 is an amazing part.
On Sun, 11 Aug 2024 22:32:38 +0100, Single Stage to Orbit <alex.buell@munted.eu> wrote:I grew up with microcomputers that had 32K of RAM and tape players.
I've got a RISCV baremetal operating system I might bring up on
this device but looking at the datasheet for the RISCV processor
used, it's only got machine mode and user mode, no supervisor mode
and no paging. It does not even support any of the Sv pagetables so
that's a challenge.
Our computer thinking evolved when CPUs filled rooms and cost
megabucks, and RAM cost a dollar per byte. Things have changed.
Virtual memory worked around the cost of RAM and encouraged
complexity and bloat. Similarly, c calling conventions gave us
hazards.
It's time to rethink things. CPUs and RAM are cheap, bloated buggy
code is expensive.
Floating point only available with the M33 cores. Hazard3 cores don't.Most interestingly enough, you can actually boot up with one RISCV
core and one ARM core, two RISCV cores or both ARM cores. Mixed
processor cores that'll be fun to see what we can do with that.
In real life, done is better than fun.
It’s a slightly odd device, isn’t it?
If you wanted to explore RISC-V then there’s more flexible options.
Long term, the ARM license may be a liability.
<https://shop.pimoroni.com/products/tiny-2350?variant=42092638699603> <https://shop.pimoroni.com/products/pga2350?variant=42092629229651>
picoplus2That's on my desk already. Had a play with it yesterday. Led fading
John Larkin <jjlarkin@highlandtechnology.com> wrote:
Long term, the ARM license may be a liability.
Arm are an investor in RPi, so not sure why they would give them a
hard time over licensing.
Andy Burns wrote:
<https://shop.pimoroni.com/products/tiny-2350?variant=42092638699603> <https://shop.pimoroni.com/products/pga2350?variant=42092629229651>
They arrived today (quite good for ordering on Sunday)
The tiny one lives up to its name, about the size of a mini SIM
card, even the PGA one is only an inch square, has nothing but 1/10" pin layout, should be good for embedding ... I'll get a picoplus2 when the second batch become available
I grew up with microcomputers that had 32K of RAM and tape players.
In some ways I agree, in other ways I disgree.
On Tue, 13 Aug 2024 20:21:26 +0100, Single Stage to Orbit <alex.buell@munted.eu> wrote:
I grew up with microcomputers that had 32K of RAM and tape players.
In some ways I agree, in other ways I disgree.
You sound like a young'n.I suppose you'll now tell us about the joys of using punched cards.
I suppose you'll now tell us about the joys of using punched cards.
I don't envy you the joys of sorting a pile of punched cards that's
been dropped on the floor ...
I suppose you'll now tell us about the joys of using punched cards.That is why you put a sequence number in col 73-80. A few passes on the
I don't envy you the joys of sorting a pile of punched cards that's
been dropped on the floor ...
On 8/14/24 07:27, Single Stage to Orbit wrote:
I suppose you'll now tell us about the joys of using punched cards.
I don't envy you the joys of sorting a pile of punched cards that's
been dropped on the floor ...
That is why you put a sequence number in col 73-80. A few passes on the sorter and no problem.
On Wed, 2024-08-14 at 11:17 +0000, Joe wrote:
On Tue, 13 Aug 2024 20:21:26 +0100, Single Stage to Orbit
<alex.buell@munted.eu> wrote:
I grew up with microcomputers that had 32K of RAM and tape players.
In some ways I agree, in other ways I disgree.
You sound like a young'n.
I suppose you'll now tell us about the joys of using punched cards.
I don't envy you the joys of sorting a pile of punched cards that's
been dropped on the floor ...
Computers used to boot a lot faster in those days. And had less bugs.
On Wed, 2024-08-14 at 11:17 +0000, Joe wrote:
On Tue, 13 Aug 2024 20:21:26 +0100, Single Stage to Orbit
<alex.buell@munted.eu> wrote:
I grew up with microcomputers that had 32K of RAM and tape players.
In some ways I agree, in other ways I disgree.
You sound like a young'n.
I suppose you'll now tell us about the joys of using punched cards.
I don't envy you the joys of sorting a pile of punched cards that's
been dropped on the floor ...
On 14/08/2024 17:55, john larkin wrote:
<snip>
Computers used to boot a lot faster in those days. And had less bugs.
Not sure about that - in the late 80's our Vax8530 took about 30 mins
for a reboot.
My X86 VMS instance in a VM on modest hardware, takes less than a minute
to reboot
On Wed, 14 Aug 2024 19:40:25 +0100, Chris Townley <news@cct-net.co.uk>The longest part was doing the startup beep.
Not sure about that - in the late 80's our Vax8530 took about 30 mins
for a reboot.
My X86 VMS instance in a VM on modest hardware, takes less than a minute
to reboot
MS-DOS was a lot faster, on a 2 MHz 8088.
The BBC Micro (2MHz 6502) was even faster booting from it's OS ROM.
Even quicker with a 8MHz NEC V30 (8086 equivalent)My X86 VMS instance in a VM on modest hardware, takes less than aMS-DOS was a lot faster, on a 2 MHz 8088.
minute to reboot
On 14/08/2024 20:07, john larkin wrote:
On Wed, 14 Aug 2024 19:40:25 +0100, Chris Townley <news@cct-net.co.uk>The longest part was doing the startup beep.
Not sure about that - in the late 80's our Vax8530 took about 30 mins
for a reboot.
My X86 VMS instance in a VM on modest hardware, takes less than a minute >>> to reboot
MS-DOS was a lot faster, on a 2 MHz 8088.
The BBC Micro (2MHz 6502) was even faster booting from it's OS ROM.
In article <v9j2na$j4rf$1@dont-email.me>, druck <news@druck.org.uk> wrote: >>On 14/08/2024 20:07, john larkin wrote:
On Wed, 14 Aug 2024 19:40:25 +0100, Chris Townley <news@cct-net.co.uk>The longest part was doing the startup beep.
Not sure about that - in the late 80's our Vax8530 took about 30 mins
for a reboot.
My X86 VMS instance in a VM on modest hardware, takes less than a minute >>>> to reboot
MS-DOS was a lot faster, on a 2 MHz 8088.
The BBC Micro (2MHz 6502) was even faster booting from it's OS ROM.
Boot times are always a somewhat interesting subjest - Yes, the Beeb
and Apple II spend more time doing the Beep at startup than anything
else. the Beeb had an advantage over the Apple II in that the filing
system was in ROM where on the Apple II it had to boot from a small PROM
on the disk controller card then load up DOS which took extra seconds...
In article <v9l0l4$vl0t$1@dont-email.me>,
Gordon Henderson <gordon+usenet@drogon.net> wrote:
In article <v9j2na$j4rf$1@dont-email.me>, druck <news@druck.org.uk> wrote: >>On 14/08/2024 20:07, john larkin wrote:
On Wed, 14 Aug 2024 19:40:25 +0100, Chris Townley <news@cct-net.co.uk> >>>> Not sure about that - in the late 80's our Vax8530 took about 30 mins >>>> for a reboot.The longest part was doing the startup beep.
My X86 VMS instance in a VM on modest hardware, takes less than a minute >>>> to reboot
MS-DOS was a lot faster, on a 2 MHz 8088.
The BBC Micro (2MHz 6502) was even faster booting from it's OS ROM.
Boot times are always a somewhat interesting subjest - Yes, the Beeb
and Apple II spend more time doing the Beep at startup than anything
else. the Beeb had an advantage over the Apple II in that the filing
system was in ROM where on the Apple II it had to boot from a small PROM
on the disk controller card then load up DOS which took extra seconds...
If you didn't care about not being in DOS, you could switch it on, hit Ctrl-Reset, and get dropped into a BASIC prompt right away. If a disk controller wasn't installed at all (it was about a year from the
introduction of the Apple II to the introduction of the Disk II floppy drive), it'd boot straight to BASIC.
After I added a hard drive to my IIe, the longest delay in starting the computer was waiting for the drive to spin up. :)
On Sun, 11 Aug 2024 22:32:38 +0100, Single Stage to Orbit <alex.buell@munted.eu> wrote:
Most interestingly enough, you can actually boot up with one RISCV core
and one ARM core, two RISCV cores or both ARM cores. Mixed processor
cores that'll be fun to see what we can do with that.
In real life, done is better than fun.
On 13 Aug 2024 14:01:07 +0100 (BST)
Theo <theom+news@chiark.greenend.org.uk> wrote:
It's easy to write a core
I wish I could take that statement back to say 1975.
Arm are an investor in RPi, so not sure why they would give them a hard
time over licensing.
Richard Kettlewell wrote:
It’s a slightly odd device, isn’t it?
If you wanted to explore RISC-V then there’s more flexible options.
Maybe the RISC-V cores are to "send a message" to ARM?
TOWARDS THE
PAPERLESS
OFFICE
I soon gave up on punching sequence numbers in source decks.
Our programs were subject to frequent modifications that required moving large blocks of code around, which meant that the sequence numbers
became meaningless.
On Wed, 14 Aug 2024 14:57:51 +0100, Ahem A Rivet's Shot wrote:
TOWARDS THE
PAPERLESS
OFFICE
People loved to laugh at that over many, many years. I’m not sure how
much paper we’re producing nowadays compared to, say, 30 years ago, but
What happened to the idea of “silicon compilers”? As I recall, they would
automate the process of turning a high-level schematic into a low-level transistor network.
On Tue, 13 Aug 2024 15:20:50 +0100, Ahem A Rivet's Shot wrote:
On 13 Aug 2024 14:01:07 +0100 (BST)
Theo <theom+news@chiark.greenend.org.uk> wrote:
It's easy to write a core
I wish I could take that statement back to say 1975.
What happened to the idea of “silicon compilers”? As I recall, they would
automate the process of turning a high-level schematic into a low-level transistor network.
On Sat, 17 Aug 2024 07:17:17 -0000 (UTC)
Lawrence D'Oliveiro <ldo@nz.invalid> wrote:
On Wed, 14 Aug 2024 14:57:51 +0100, Ahem A Rivet's Shot wrote:
TOWARDS THE
PAPERLESS
OFFICE
People loved to laugh at that over many, many years. I’m not sure how
much paper we’re producing nowadays compared to, say, 30 years ago, but
Oh we've pretty much achieved it by now, more than forty years on
from that sign.
On Wed, 14 Aug 2024 16:52:27 GMT, Charlie Gibbs wrote:
I soon gave up on punching sequence numbers in source decks.
Our programs were subject to frequent modifications that required moving
large blocks of code around, which meant that the sequence numbers
became meaningless.
This is why you didn’t have the sequence go up in steps of 1, but use larger steps, like say 100. That made it easier to insert new cards with in-between numbers.
On 17/08/2024 09:15, Ahem A Rivet's Shot wrote:
On Sat, 17 Aug 2024 07:17:17 -0000 (UTC)
Lawrence D'Oliveiro <ldo@nz.invalid> wrote:
On Wed, 14 Aug 2024 14:57:51 +0100, Ahem A Rivet's Shot wrote:Oh we've pretty much achieved it by now, more than forty years on
TOWARDS THE
PAPERLESS
OFFICE
People loved to laugh at that over many, many years. I’m not sure how
much paper we’re producing nowadays compared to, say, 30 years ago, but >>
from that sign.
Its been hard, but by dint of scanning almost every bit of paper I get,
I am nearly there.
On Mon, 12 Aug 2024 18:41:59 +0200, Lasse Langwadt <llc@fonz.dk>
wrote:
On 8/11/24 23:07, John Larkin wrote:
On Sun, 11 Aug 2024 14:04:36 -0700, John Larkin
<jjlarkin@highlandtechnology.com> wrote:
On Sun, 11 Aug 2024 21:45:42 +0100, Andy Burns <usenet@andyburns.uk>
wrote:
Surprised nobody has mentioned the Pico2 boards (based on RP2350A or >>>>> RP2350B chips, instead of RP2040).
2x ARM cores plus 2x RISC-V cores (perm any 2 from 4)
150 MHz with FPU instead of 133MHz without
lower power consumption
more I/O pins (B model only?)
I really ought to buy a couple for tinkering ...
official boards not available yet, but 3rd party boards are, e.g.
<https://shop.pimoroni.com/products/tiny-2350?variant=42092638699603> >>>>> <https://shop.pimoroni.com/products/pga2350?variant=42092629229651>
As of now, Digikey shows no stock on the Pico2 and doesn't recognize
the RP2350 chip as a product. Ditto Mouser.
The fast floats look great. I wonder how fast they are.
The RP2350 data sheet is 1347 pages!
read the part on how the build in buck converter needs a custom inductor
with polarity marking to work, and tell there is something seriously
wrong with it
The polarized inducor is strange. I'd expect that a small shielded
inductor would work fine. It is interesting to have a switching
regulator on a CPU chip... near a 12-bit ADC!
On 13/08/2024 12:43 pm, John Larkin wrote:
On Mon, 12 Aug 2024 18:41:59 +0200, Lasse Langwadt <llc@fonz.dk>
wrote:
On 8/11/24 23:07, John Larkin wrote:
On Sun, 11 Aug 2024 14:04:36 -0700, John Larkin
<jjlarkin@highlandtechnology.com> wrote:
On Sun, 11 Aug 2024 21:45:42 +0100, Andy Burns <usenet@andyburns.uk> >>>>> wrote:
Surprised nobody has mentioned the Pico2 boards (based on RP2350A or >>>>>> RP2350B chips, instead of RP2040).As of now, Digikey shows no stock on the Pico2 and doesn't recognize >>>>> the RP2350 chip as a product. Ditto Mouser.
2x ARM cores plus 2x RISC-V cores (perm any 2 from 4)
150 MHz with FPU instead of 133MHz without
lower power consumption
more I/O pins (B model only?)
I really ought to buy a couple for tinkering ...
official boards not available yet, but 3rd party boards are, e.g.
<https://shop.pimoroni.com/products/tiny-2350?variant=42092638699603> >>>>>> <https://shop.pimoroni.com/products/pga2350?variant=42092629229651> >>>>>
The fast floats look great. I wonder how fast they are.
The RP2350 data sheet is 1347 pages!
read the part on how the build in buck converter needs a custom inductor >>> with polarity marking to work, and tell there is something seriously
wrong with it
The polarized inducor is strange. I'd expect that a small shielded
inductor would work fine. It is interesting to have a switching
regulator on a CPU chip... near a 12-bit ADC!
I don't think they know much about how to do ADCs yet.
Have a look at the performance of the RP2040 ADC - it is awful!
http://pico-adc.markomo.me/
I hope the new one is better.
On Wed, 2024-08-14 at 11:17 +0000, Joe wrote:
On Tue, 13 Aug 2024 20:21:26 +0100, Single Stage to Orbit
<alex.buell@munted.eu> wrote:
I grew up with microcomputers that had 32K of RAM and tape players.
In some ways I agree, in other ways I disgree.
You sound like a young'n.
I suppose you'll now tell us about the joys of using punched cards.
I don't envy you the joys of sorting a pile of punched cards that's
been dropped on the floor ...
I like the Pi for more reasons than the cost. The chips have long-term availability guarentees, the documentation is excellent, and there are zillions of kids out there who are familiar with the Pi culture.
Am 13.08.24 um 17:55 schrieb John Larkin:
I like the Pi for more reasons than the cost. The chips have long-term
availability guarentees, the documentation is excellent, and there are
zillions of kids out there who are familiar with the Pi culture.
I could not find a CPU chip manual in an hour for my new 8GB RP5
that allowed me to use SPI, so I shelved it and went with the old
BBB and its PRU. So far about documentation excellence.
Gerhard
I decided to stop with newer Raspberry Pis after this 8 GB Pi4 I am using to post this.
A 35 dollar HD TV satellite box is a faster better media player,
Pis take ever more power..
Is not Pi5 a downgraded Pi4?
On 22/08/2024 07:37, Jan Panteltje wrote:
I decided to stop with newer Raspberry Pis after this 8 GB Pi4 I am using to post this.
A 35 dollar HD TV satellite box is a faster better media player,
Try a media optimised OS such as Kodi, rather than a general purpose
distro if you want to use a Pi as a media player.
Pis take ever more power..
Don't confuse the availability of a larger power supply with the Pi 5
taking more power - it's not much different to the Pi 4. However, as you >*could* attach 4 USB devices and a PCIe device, the PSU is rated to cope >with the maximum current all of those devices could use simultanously.
If you won't be doing that, you can use the Pi 4 PSU.
Is not Pi5 a downgraded Pi4?
No, it's a new SOC which is about 3x faster than a Pi 4, and can use
NVME SSDs and other PCIe devices.
In the old days I had to buy a decoder key from Raspberry to even look
at mpeg!
On Fri, 23 Aug 2024 06:19:06 GMT, Jan Panteltje wrote:
In the old days I had to buy a decoder key from Raspberry to even look
at mpeg!
Presumably that was only to activate the decoder hardware. Otherwise
FFmpeg, VLC etc could play it just fine, just with a bit more CPU usage.
On 22/08/2024 07:37, Jan Panteltje wrote:
Pis take ever more power..
Don't confuse the availability of a larger power supply with the Pi 5
taking more power - it's not much different to the Pi 4. However, as you *could* attach 4 USB devices and a PCIe device, the PSU is rated to cope with the maximum current all of those devices could use simultanously.
If you won't be doing that, you can use the Pi 4 PSU.
I think that as a desktop machine Pi 4s and 5s power consumption is approaching that of a good intel chipset *for equivalent performance*.
On Fri, 23 Aug 2024 06:19:06 GMT, Jan Panteltje wrote:
In the old days I had to buy a decoder key from Raspberry to even look
at mpeg!
Presumably that was only to activate the decoder hardware. Otherwise
FFmpeg, VLC etc could play it just fine, just with a bit more CPU usage.
On Fri, 23 Aug 2024 06:19:06 GMT, Jan Panteltje wrote:
In the old days I had to buy a decoder key from Raspberry to even look
at mpeg!
Presumably that was only to activate the decoder hardware. Otherwise
FFmpeg, VLC etc could play it just fine, just with a bit more CPU usage.
On Fri, 23 Aug 2024 10:36:20 +0100
The Natural Philosopher <tnp@invalid.invalid> wrote:
I think that as a desktop machine Pi 4s and 5s power consumption is
approaching that of a good intel chipset *for equivalent performance*.
The rise of ARM caused Intel and AMD to pay a *lot* more attention
to power consumption which has indeed resulted in the gap closing
especially at desktop levels of performance.
Too much bloat these days and Linux with all the rathead shit is
becoming a nuisance.
We went to the moon in the sixties of last century and came back with computing power less than a Raspberry.
Now astronuts get stuck on the ISS with billions of dollars and
sup[p]er computers to do the work.
We went to the moon in the sixties of last century and came back
with computing power less than a Raspberry.
Now astronuts get stuck on the ISS with billions of dollars and sup[p]er computers to do the work.
Boeing are busy acquiring a reputation of careless engineering.Primarily due to acquiring beancounters from the ruins of McDonnell
On Fri, 23 Aug 2024 10:33:21 GMT, Jan Panteltje wrote:
Too much bloat these days and Linux with all the rathead shit is
becoming a nuisance.
Linux can be as small as you want. Look at Damn Small Linux, for example. >You can actually build a kernel to run on certain CPUs with no memory- >management hardware.
We went to the moon in the sixties of last century and came back with
computing power less than a Raspberry.
There was actually a whole lot of computing power on the ground, in the
form of those IBM mainframes, backing up the guys in space. Everything
they did had to be managed in coordination with ground control, all the >steps worked out in advance.
Now astronuts get stuck on the ISS with billions of dollars and
sup[p]er computers to do the work.
Bit more Government management of the process back then, bit more trust to >private corporations like Boeing, with its stellar reputation for >relentlessly pursuing reliability over profits, these days.
Coincidence? You be the judge.
But chances are by the time they arrive at Mars they need Chinese Visa
and money, pay landing rights.
the race to more MIPS is likely to drive adoption of
nuclear power
I don't see data centres 'throttling back' servers after sunset, or on
calm days...
Hohmann worked out the details of travel around the solar system
using the computing power in his head and the storage afforded by a
pencil and paper. The computing requirements for space travel are not
that large.
Boeing are busy acquiring a reputation of careless engineering.
On Sat, 24 Aug 2024 12:32:59 GMT Jan Panteltje <alien@comet.invalid>
wrote:
But chances are by the time they arrive at Mars they need Chinese Visa
and money, pay landing rights.
<splort!> I always thought that that was one of the things Jos
Whedon got right in Firefly - two languages in space Chines and English
with people speaking a pidgin of both.
On Wed, 2024-08-14 at 11:17 +0000, Joe wrote:
On Tue, 13 Aug 2024 20:21:26 +0100, Single Stage to Orbit
<alex.buell@munted.eu> wrote:
I grew up with microcomputers that had 32K of RAM and tape players.
In some ways I agree, in other ways I disgree.
You sound like a young'n.
I suppose you'll now tell us about the joys of using punched cards.
I don't envy you the joys of sorting a pile of punched cards that's
been dropped on the floor ...
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